模拟电路的性能紧密依赖于版图的寄生参数和匹配特性 .提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及 STACK内连线的不匹配的模型 .基于该模型 ,一种新的 STACK生成方法用来控制版图的寄生参数和匹配特性 ,优化 STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图 .一个 OPA电路的例子说明了所提出的版图优化方法可以提高诸如单位增益带宽和相位余量等电路性能 The performance of the analog circuit is closely dependent on the parasitic and matching characteristics of the layout. Models are proposed to describe the distributed parasitic capacitances and parasitics mismatch due to process gradients and the mismatch between STACK interconnects. Based on this Model, a new STACK generation method is used to control the parasitics and matching characteristics of the layout, to optimize the shape of the STACK and to ensure that the corresponding Eulerian diagrams are generated for the given analog circuit module. An example of an OPA circuit illustrates the proposed The layout optimization method can improve the circuit performance such as unity gain bandwidth and phase margin