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为了提高硬件使用率、减少芯片面积,提出了一种包括4×4正反变换、4×4哈达码变换及2×2哈达码变换在内的多变换编码结构.通过将这几种变换算法化简,并且研究它们之间的相似性,将处理单个变换的结构合并成一个高性能多变换编码结构.采用SMIC 0.18μm CMOS工艺,该结构最高工作频率可达200 MHz,并在消耗3704门电路的情况下,达到800×106 pixel/s的吞吐率.结果表明,该设计的吞吐率和电路规模的比值DTUA比参考设计至少提高了40.28%,并且在62.9 MHz的频率下支持分辨率为4 096×2 048、刷新频率为30 Hz的视频实时解码需求,从而有助于降低功耗.
In order to improve the hardware utilization and reduce the chip area, a multi-transform coding structure including 4 × 4 forward-reverse transform, 4 × 4 Hadamard transform, and 2 × 2 Hadamard transform is proposed.Through these transformation algorithms Simplify, and study the similarity between them, and combine the structure of a single transform into a high-performance multi-transform coding structure with a maximum operating frequency of up to 200 MHz in a SMIC 0.18μm CMOS process and consume 3704 gates Circuit, the throughput of 800 × 106 pixel / s is achieved.The results show that the ratio of throughput to circuit size of the design is increased by at least 40.28% compared with the reference design, and the resolution at the frequency of 62.9 MHz is 4 096 × 2 048, refresh rate of 30 Hz video real-time decoding needs, thereby helping to reduce power consumption.