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A novel test approach for interconnect resources (IRs) in field programmable gate arrays (FPGA) has been proposed.In the test approach,SBs (switch boxes) of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks (CLBs) in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip (SoC) hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
A novel test approach for interposing resources (IRs) in field programmable gate arrays (FPGAs) has been proposed. In the test approach, SBs (switch boxes) of IRs in FPGA has been utilized to test IRs. Morerther, configurable logic blocks (CLBs ) in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result, IRs can be scanned maximally with minimum configuration patterns.In the experiment, an in-house developed FPGA test system based on system-on-chip (SoC) hardware / software verification technology has been applied to test XC4000E family of Xilinx. The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.