论文部分内容阅读
A highly integrated monolithic Multi-Service Transport Platform (MSTP) Application Specified Integrated Circuit (ASIC) MSEOSX8-6 has been fabricated with 0.18μm CMOS technology incorporating 26×106 transistors. The chip is designed to provide standard framing and mapping of 10/100/1000Mbit/s Ethernet, Resilient Packet Ring (RPR) and E1 traffics into protected Synchronous Digital Hierarchy (SDH) STM-1 transport payloads using hitless rate adaptation for optimum bandwidth utilization. It consumes 4W of power on average and utilizes 756 pin enhanced BGA package.