论文部分内容阅读
采用GF 0.18μm标准CMOS工艺,设计并实现了一种12 bit 20 MS/s流水线模数转换器(ADC)。整体架构采用第一级4 bit与1.5 bit/级的相结合的方法。采用改进的增益数模单元(MDAC)结构和带驱动能力的栅自举开关来提高MDAC的线性度和精度。为了降低子ADC的功耗,采用开关电容式比较器。仿真结果表明,优化的带驱动的栅自举开关可减小采样保持电路(SHA)的负载压力,有效降低开关导通电阻,降低电路的非线性。测试结果表明:在20 MS/s的采样率下,输入信号为1.234 1 MHz时,该ADC的微分非线性(DNL)为+0.55LSB/-0.67LSB,积分非线性(INL)为+0.87LSB/-0.077LSB,信噪比(SNR)为73.21 dB,无杂散动态范围(SFDR)为69.72 dB,有效位数(ENOB)为11.01位。芯片面积为6.872 mm2,在3.3 V供电的情况下,功耗为115 mW。
A 12-bit, 20 MS / s pipelined analog-to-digital converter (ADC) was designed and implemented using a GF 0.18μm standard CMOS process. The overall architecture uses the first level of 4 bit and 1.5 bit / level combination of methods. Improved MDAC linearity and accuracy are achieved with a modified Gain-Modulus Unit (MDAC) architecture and a gate-driven switch with drive capability. In order to reduce sub-ADC power consumption, the use of switched capacitor comparator. The simulation results show that the optimized bootstrapped switch with gate drive can reduce the load pressure of the sample-and-hold circuit (SHA), reduce the on-resistance of the switch and reduce the nonlinearity of the circuit. The test results show that the ADC has a differential non-linearity (DNL) of + 0.55LSB / -0.67LSB and an integrated nonlinearity (INL) of + 0.87LSB at an input signal of 1.234 1 MHz at a sampling rate of 20 MS / s /-0.077LSB, the signal-to-noise ratio (SNR) is 73.21 dB, the SFDR is 69.72 dB, and the effective number of bits (ENOB) is 11.01 bits. The chip area is 6.872 mm2 and consumes 115 mW at 3.3 V.