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现有文献对变采样周期锁相环(variable sampling period PLL,VSP_PLL)的原理分析尚不深入,且未给出其调节器设计方法。通过与传统的基于同步旋转坐标系锁相环(synchronous reference frame PLL,SRF_PLL)对比,明晰了VSP_PLL的控制机制,揭示了其内在联系。建立了VSP_PLL的离散域数学模型,分析了采用不同调节器的VSP_PLL环路特性,得出了调节器(包括其型式及参数)的优化设计方法。实验结果验证了所设计的VSP_PLL在电网电压出现谐波、不平衡、幅值及频率瞬变的情况下均可准确快速地锁相。
The existing literature does not analyze the principle of the variable sampling period PLL (VSP_PLL), and its regulator design method is not given. Compared with the traditional synchronous reference frame PLL (SRF_PLL), the control mechanism of VSP_PLL is clarified and its internal relations are revealed. The discrete domain mathematical model of VSP_PLL is established. The VSP_PLL loop characteristics of different regulators are analyzed, and the optimal design method of regulator (including its type and parameters) is obtained. The experimental results verify that the designed VSP_PLL can be locked accurately and quickly when the grid voltage appears harmonic, unbalance, amplitude and frequency transient.