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采取破坏信息读出的动态MOS单晶体管存贮器单元,其读出信号随着单元面积的减小而降低。为了获得所要求的小面积的单元,就必须用具有高比电容的器件来作存贮电容器,与此同时,还需要有灵敏的刷新放大器及噪声补偿阵列。因此,对于硅栅工艺的单元设计,建议用场致非平衡反型层作电极的存贮电容器。提出了一种用作灵敏刷新放大器的选通触发器,它的两个输入结点每个都可用作一条位线。如此而获得的对称阵列,不仅灵敏度高(输入电压差的不确定范围大约是晶体管阈值电压的0.3倍)和不以工艺参数为转移,而且还允许用触发器每端的一条伪字线(与伪单元一起)作噪声补偿。已用硅栅工艺实现了各种单元和刷新放大器,具有1600平方微米(约2.6平方密耳)面积的单元已成功地以350毫微秒的读/写周期时间工作(在每条位线64个单元或者每一放大器128个单元时,存贮电容0.134pF,位线电容0.32pF)。
Dynamic MOS single transistor memory cells that read corrupt information are used, and the readout signal decreases as the cell area decreases. In order to obtain the required small area of the unit, it is necessary to use a device with a high specific capacitance for the storage capacitor, while also requiring a sensitive refresh amplifier and noise compensation array. Therefore, for the cell gate technology Si design, it is recommended to use the field of non-equilibrium inversion layer for the storage capacitor electrode. A gated flip-flop is proposed for use as a sensitive refresh amplifier, with each of its two input nodes acting as a bit line. The symmetrical array thus obtained not only has high sensitivity (the uncertainty of the input voltage difference is about 0.3 times the threshold voltage of the transistor) and does not shift with the process parameters, but also allows the use of a dummy word line on each side of the flip- Unit together) for noise compensation. Various cells and refresh amplifiers have been implemented with a silicon gate process and cells with an area of 1600 square microns (about 2.6 square mil) have been successfully operated with a read / write cycle time of 350 nanoseconds (at 64 Cells or 128 cells per amplifier, storage capacitance 0.134pF, bitline capacitance 0.32pF).