设计并实现了一种14位50 MS/s流水线ADC.采用无采保放大器的前端电路和运放共享技术,在达到速度及精度要求的同时降低了功耗.该流水线ADC采用0.13tm标准CMOS工艺实现,芯片尺寸为2.7 mm×2.1 mm.在电源电压为1.2V、采样速率为50 MS/s、模拟输入信号频率为28 MHz的条件下进行测试.结果表明,该ADC的功耗为91.2 mW,SFDR为82.39dBFS,SNR为72.45 dBFS,SNDR为71.13 dB,ENOB为11.52 bit,THD为-81.28 dBc,DNL在±1 LSB以内,INL在±3 LSB以内,品质因子FOM为0.62 pJ/step.“,”A 14 bit 50-MS/s pipelined ADC was designed and implemented.Due to the fact that the proposed ADC was based on the techniques of SHA-less and op-amp sharing,the required speed and precision could be achieved while the power consumption was reduced.This ADC was fabricated in a 0.13 μm standard CMOS process with a chip size of 2.7 mm× 2.1 mm.The implemented ADC was measured under different input frequencies with a sampling rate of 50 MS/s.The results showed that it consumed 91.2 mW from a 1.2 V supply.At 28 MHz input,the measured SFDR,SNR,SNDR,ENOB,and THD of the ADC was 82.39 dBFS,72.45 dBFS,71.13 dB,11.52 bit,-81.28 dBc respectively.The measured DNL and INL were optimized to ±1 LSB and ±3 LSB respectively,and the FOM was 0.62 pJ/step.