针对现有面阵CCD时序驱动调试比较困难、灵活性较差的问题,设计出一种基于FPGA的面阵CCD时序发生器。以行间转移型面阵CCD传感器ICX229AK为例,对其工作原理及驱动时序进行了详细的分析,选用FPGA开发板作为硬件设计平台,采用两重循环嵌套对其时序进行硬件描述,并对时序发生器进行了仿真与验证。结果表明,设计的时序发生器灵活性得到了较大的提升。 Aiming at the problem that the existing array CCD timing-driven debugging is more difficult and less flexible, an FPGA-based area array CCD timing generator is designed. Taking the interline CCD sensor ICX229AK as an example, the working principle and driving sequence are analyzed in detail. The FPGA development board is selected as the hardware design platform, and the two loops are nested to describe its timing. Timing generator was simulated and verified. The results show that the design of timing generator flexibility has been greatly improved.