提出了一种片内信号间的相位检测与同步电路。该电路通过检测信号间的相位信息,连续调整其中一个信号的延迟,从而保持信号与信号之间始终处于设定的相位同步关系。介绍了相位检测与同步电路的原理及结构,给出了每一个模块的具体电路结构并加以分析。基于SMIC 65nm CMOS工艺,采用Cadence Spectre进行仿真,结果表明,电路可产生16个固定的相位关系,工作在1~4GHz的宽频范围,在4GHz工作频率时功耗为52mW,而芯片尺寸为450μm×450μm。 An on-chip phase detection and synchronization circuit is proposed. The circuit continuously adjusts the delay of one of the signals by detecting the phase information between the signals so as to keep the signal and the signal always in the set phase synchronization relationship. The principle and structure of phase detection and synchronization circuit are introduced. The concrete circuit structure of each module is given and analyzed. Based on the SMIC 65nm CMOS process and Cadence Specter simulation, the results show that the circuit can generate 16 fixed phase relationship, work in the wide frequency range of 1 ~ 4GHz, power consumption is 52mW at 4GHz operating frequency, and the chip size is 450μm × 450 μm.