A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfiguration analysis of algorithms, the design of reconfigurable processing units and a new reconfigurable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the operating frequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance. A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfiguration analysis of algorithms, the design of reconfigurable processing units and a new reconfigurable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the operating frequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Our design can achieve a higher performance.