校验历来都是FPGA设计流程的一个组成部分。在门级原理医输入设计流程中，设计输入后通常对设计进行功能仿真，布局和布线后对设计进行时序仿真。几年前，FPGA的平均密度接近1．5万系统门，设计者采用这些门级的设计方法可以满足上市时间的要求。但是平均门数以每年按指数级跳 Verification has always been an integral part of the FPGA design flow. In the gate-level principle of medical input design flow, the design input is usually functional simulation of the design, layout and layout of the timing simulation of the design. A few years ago, FPGAs averaged nearly 15,000 system gates, and designers used these gate-level design approaches to meet time-to-market requirements. However, the average number of gates jumps exponentially each year